Node creation is done by selecting a node from the component menu in the side bar (on the left).
The nodes are outlined in blue.
After clicking on one of these nodes, click in the edit window to place the node.
The location of the cursor is aligned to the nearest grid unit.
This adjustment can be controlled with the
"Grid" preferences (in menu File / Preferences..., "Display" section, "Grid" tab).
When placing a node, the cursor points to the anchor point of the newly created node.
This is the center (for primitives) or the location of the cell-center (for cell instances).
Cell instances can change their anchor point by moving the Cell-Center node inside of their layout
(see Section 3-3).
Besides basic components, there are special entries in the component menu for creation of additional nodes:
- The "Cell" button displays a list of cell instances that can be created
(see Section 3-3).
- The "Pure" button (only available in layout technologies) lets you place pure-layer nodes
(see Section 6-10-1).
- The "Spice" button (only available in schematics) lets you place Spice primitives
(see Section 9-4-3).
- The "Misc" button has a collection of special objects that can be created.
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These objects can be created with the "Misc" button:
- Cell Instance brings up a dialog to select an instance to place
(see Section 3-3).
- Annotation Text places a node that contains only text
(see Section 6-8-1).
- Layout Text... brings up a dialog to create text from layout nodes
(see Section 6-10-3).
- Annular Ring... brings up a dialog to create circular shapes
(see Section 6-10-3).
- Cell Center places a node that defines the origin of the cell
(see Section 3-3).
- Essential Bounds places a node that defines the corners of the cell's essential bounds
(see Section 7-6-3).
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- Spice Code places a text-only node that will be inserted into Spice decks
(see Section 9-4-3).
- Spice Declaration places a text-only node that will be inserted into Spice decks near the top
(see Section 9-4-3).
- Verilog Code places a text-only node that will be inserted into the code area of Verilog decks
(see Section 9-4-2).
- Verilog Declaration places a text-only node that will be inserted into the declaration area of Verilog decks
(see Section 9-4-2).
- Simulation Probe places a node that can be used to display simulation results
(see Section 4-12-1).
- DRC Exclusion places a node that covers DRC errors and causes them to be ignored
(see Section 9-2-6).
- Invisible Pin places an invisible-pin node
(see Section 7-6-3).
- Universal Pin places an universal-pin node
(see Section 7-6-3).
- Unrouted Pin places an unrouted-pin node
(see Section 7-6-3).